Booting a Rigol DHO900 to a live trace in 12 seconds

CH1Where the time went

The DHO's acquisition FPGA is a Xilinx Zynq. At power-on it runs a factory "golden" image; the scope then programs an LMX2582 PLL for the ADC clock and tells the Zynq, over SPI, to multiboot into the real acquisition image. Only then does the FPGA appear on PCIe, and the scope software can start.

The stock firmware never asks the FPGA whether it is ready. It sleeps: 5 seconds inside the boot tool and another 10 in the start-up script, and it holds the boot command until the system has been up about 17 seconds. That is safe, and slow. Our first images copied those waits, so the FPGA step alone took over 15 seconds.

CH2Asking instead of sleeping

The Zynq has no "done" pin the processor can see, so the only readiness signal is the FPGA itself: its PCIe endpoint appearing, and the version stamp the acquisition image reports. NovaOS now:

• sends the multiboot command as soon as the PLL is programmed;
• probes for the PCIe endpoint from 2 seconds later;
• reads the version stamp to confirm the update image really loaded, and not the golden image, and sends the boot command again if it didn't;
• falls back to the stock timing only if all of that fails.

Over seven measured boots the update image loaded on the first command every time, with the endpoint found 2.4 to 2.8 seconds after it. The FPGA step went from over 15 seconds to 2.0.

CH3A kernel bug on the way

Probing early means a probe can miss. Testing that case found a real bug in the 6.12 BSP's RK3399 PCIe host driver: after one failed link training, its error path released the PCIe PHY twice. The PHY's reference count went negative, and from then on every attempt failed with "phy_power_on was called before phy_init" and a PLL lock timeout, until a reboot. We fixed the error path the way kernel.org's driver handles it, and proved it on the unit: a deliberately failed training, then a successful one, without a reboot.

CH4The rest of the boot

• The serial console printed 39 kB synchronously at 115200 baud, about 3.4 seconds. Normal boots now print only warnings; everything is still in the journal.
• The kernel image went from 39.7 to 28.2 MB by building drivers the scope never needs at boot as modules. Rigol's U-Boot reads the kernel raw, with no decompressor, at about 10 MB/s, so size is time.
• The FPGA service waited for udev to name the calibration partition. The early boot stage now mounts it, read-only, before systemd starts, so the FPGA starts about 2 seconds earlier.
• systemd's own start stalled about a second reading its libraries from the SD card in small random reads. One sequential read-ahead, started before systemd, cut that gap to 0.84 seconds.

Where it stands

The boot screen now shows these steps as a progress bar, timed from that unit's own previous boots. The next cut is already in testing: the PLL is programmed with 50 ms between each of its 46 register writes, while its datasheet asks for nanoseconds. We'll only switch it after the clock's lock and accuracy check out on repeated boots.

Measured on our own DHO924S. Stock's boot to a live trace is being measured the same way for a fair comparison.