An instrument of our own: no screen and no knobs, driven by an AI agent or any program over Ethernet or USB, and an FPGA bring-up bench in the same box. This page tracks where the design stands, the range we are aiming at, the open projects we learn from and what it costs to build. Every figure here is a target until a measurement replaces it.
| Step | Status | Where it stands |
|---|---|---|
| The agent interface | running | Proven before any board exists: our MCP server drives the Rigol scopes on our bench, so the calls the instrument will serve are already in use. |
| Scope software | running | NovaOS, our Linux 6.12 stack, runs two Rigol scopes every day (DHO, MHO). The instrument gets the same engine with a new hardware backend. |
| Specification | draft 6 | Targets, parts, cost and power for every card, generated from data with a source on each line. Draft 6, 7 Oct 2026. |
| Platform: mainboard, cards, core module | in design | One mainboard with a card backplane and one clock tree, a card standard every card plugs into, and our own core module on a Rockchip RK3576 as the host. |
| High-speed acquisition card | in design | TI's ADC12DJ5200RF into an AMD Kintex UltraScale+ Gen 2 FPGA (XC2KU030P) with its own LPDDR5 record memory, built from the makers' reference designs. AMD's Gen 2 parts sample from Q4 2026; development starts on AMD's Spartan UltraScale+ kit. |
| The board-port pod | next | The first board to build: the bring-up electronics on their own (JTAG, console, configuration pins, logic, two supplies), useful beside any scope the day it works. |
| Link-probe prototype | planned | On FPGA boards we already have: lock a transceiver to a running serial lane and map its eye with the transceiver's own eye scan. |
| Card timing | planned | Two MHO934s on one clock, every card's delay measured at power-up and padded to the slowest, proven before our own backplane exists. |
| Front-end and clock cards | planned | Measured on the bench against the MHO: bandwidth with a LibreVNA, noise, step response, channel-to-channel skew. |
| Base unit | planned | Enclosure, USB-C and PoE power, the physical generator-enable switch; then stacking units to 8 and 16 channels. |
| Card | Target |
|---|---|
| General acquisition | 4 channels; 1 GS/s 8-bit on 1 channel (250 MS/s on 4), 640 MS/s 12-bit, 105 MS/s 14-bit; 350 MHz; 1 mV/div to 10 V/div |
| High speed | 2 × 5.2 GS/s or 1 × 10.4 GS/s, 12-bit; 3 GHz at 50 Ω; 16 GB record memory (about 0.77 s at 10.4 GS/s) |
| Link probe | 4 transceiver lanes, 0.5 to 10.3 Gb/s (12.5 with a faster grade): lock, 2-D eye scan, bit-error rate, protocol decode |
| Bring-up | 8 logic lines on the port, 16 on a pod at 500 MS/s; JTAG to 30 MHz; console to 12 Mbaud; 2 supplies, 0.8 to 12 V, 2 A each; 1 generator channel to 25 MHz |
| Connections | Gigabit Ethernet with PoE (802.3bt) or USB-C (power and a driverless network adapter); 10 MHz reference and trigger in and out; a sync port for stacking units |
Our day job is FPGA video processing: serial lanes to 12.5 Gb/s, video LVDS above 1 Gb/s per pair, DDR3 to 1866 MT/s. A scope that only matched the ThunderScope or the MHO934 would not see those signals, so the general card covers the everyday class and the high-speed card goes two classes up. For each class we sized every link of the chain (front end, ADC, ADC-to-FPGA lanes, record memory, clock jitter) against the parts' datasheets so no link holds the others back.
| Class | Bandwidth · sample rate · bits | Built in this class by (published) | Ours |
|---|---|---|---|
| Entry | 350 MHz · 1 GS/s · 8-bit | ThunderScope (ADI HMCAD1520 + Artix-7); Siglent SDS1000X-E (HMCAD1511 + Zynq); Rigol DHO800 / DHO900 | the general card |
| Mid | 1 GHz · 6.4 GS/s · 12-bit | R&S MXO 4 (TI ADC12DL3200 + Zynq UltraScale+); Siglent SDS6000 Pro (Kintex UltraScale+); Rigol MHO5000 | – |
| High | 3 GHz · 10.4 GS/s · 12-bit | Siglent SDS7000A; Rigol DS70000; Keysight MXR and Tektronix 6 Series B (custom ADC chips) | the high-speed card |
| Top | 4 GHz · 20 GS/s · 12-bit | Siglent SDS7000A; R&S RTP; Keysight UXR (custom chips) | the same FPGA family's larger part reaches it |
| ThunderScope | Rigol MHO934 | Ours (targets) | |
|---|---|---|---|
| Analog channels | 4 | 4 | 4 general + 2 high-speed |
| Sample rate | 1 GS/s 8-bit, 500 MS/s 12-bit | 4 GSa/s, 12-bit | 10.4 GS/s 12-bit on the high-speed card |
| Bandwidth | 350 MHz on 1 channel, 100 MHz on 4 | 350 MHz | 3 GHz high-speed, 350 MHz general |
| Multi-Gb/s links | none | none | 4 lanes: eye scan, BER, decode |
| Memory | the PC's RAM | 100 Mpts (500 Mpts option) | 16 GB on the high-speed card |
| Host | your PC over Thunderbolt or PCIe | Android on an RK3399, 7″ touch screen | its own: NovaOS on an RK3576 |
| Agent interface | no | SCPI (our MCP server drives it) | MCP, JSON, SCPI |
| Price | $1,099 (PCIe) / $1,299 (Thunderbolt), shipping December 2026 | about $999 to $1,319 retail | not set (below) |
ThunderScope from its Crowd Supply page; MHO934 from retailer specifications; the class examples from the makers' data sheets and published teardowns. Seen October 2026.
The price is not set: it comes from what the people who would use it tell us, and from what each card costs to build. Where the parts stand today, at prototype quantity, parts only (no assembly, test or margin):
| What | Parts estimate | Notes |
|---|---|---|
| Board-port pod | about $150 | the bring-up electronics in a small USB box, used beside any scope |
| General acquisition card | about $260 | 4 channels, the entry class |
| High-speed acquisition card | about $2,900 and up | the ADC and the Gen 2 FPGA are most of it; the FPGA has no price yet |
| Full instrument, every card | about $4,500 | about 70 % of it from real quotes, the rest estimates |
So the realistic shapes are a low-cost pod first, an entry instrument with the general card, and the high-speed card as the step up. Tell us which of those you would buy and what you would pay: brady@aioscilloscope.com.